Free Coupon Discount - VSD - Functional Verification Using Embedded-UVM - Part 1, Introduction to Discrete Event Simulation Technology, Functional Verification, Getting acquainted with Simulation tools
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Created by Kunal Ghosh, Puneet Goel
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What you'll learn
- SoC design flow, role of Functional Verification
- Logic Modeling, Introduction to Verilog
- Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
- Simulation Technology, Discrete Event Simulation
- Verification Trends and Challenges
- Concepts and Principles of Functional Verification
- Testbench Architecture and Components
- Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms
- Requirements
- Should be good with digital electronics
- Should be good with Linux/UNIX basic commands
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